Old stuff/ecole_etude_fac_de_pau/licence_3/archi/ual.v
(Deskargatu)
//: version "1.8.6"
module soustr();
//: interface /sz:(40, 40) /bd:[ ]
//: enddecls
endmodule
module additi(s, b, a);
//: interface /sz:(40, 40) /bd:[ ]
input [7:0] b; //: /sn:0 {0}(390,101)(438,101)(438,154)(334,154)(334,181){1}
output [7:0] s; //: /sn:0 {0}(326,294)(318,294)(318,210){1}
input [7:0] a; //: /sn:0 {0}(168,100)(197,100)(197,154)(302,154)(302,181){1}
wire w3; //: /sn:0 {0}(342,195)(470,195){1}
wire w2; //: /sn:0 {0}(235,195)(294,195){1}
//: enddecls
//: output g3 (s) @(323,294) /sn:0 /w:[ 0 ]
//: input g2 (b) @(388,101) /sn:0 /w:[ 0 ]
//: input g1 (a) @(166,100) /sn:0 /w:[ 0 ]
add g0 (.A(a), .B(b), .S(s), .CI(w3), .CO(w2)); //: @(318,197) /sn:0 /w:[ 1 1 1 0 1 ]
endmodule
module multt(s, b, a);
//: interface /sz:(40, 40) /bd:[ ]
input [7:0] b; //: /sn:0 /dp:1 {0}(235,159)(235,122)(279,122)(279,97)(263,97){1}
output [7:0] s; //: /sn:0 {0}(219,188)(219,271)(245,271){1}
input [7:0] a; //: /sn:0 /dp:1 {0}(203,159)(203,124)(148,124)(148,97)(138,97){1}
//: enddecls
//: output g3 (s) @(242,271) /sn:0 /w:[ 1 ]
mult g2 (.A(a), .B(b), .P(s)); //: @(219,175) /sn:0 /w:[ 0 0 0 ]
//: input g1 (b) @(261,97) /sn:0 /w:[ 1 ]
//: input g0 (a) @(136,97) /sn:0 /w:[ 1 ]
endmodule
module ual; //: root_module
wire w7; //: /sn:0 {0}(231,415)(241,415){1}
wire [7:0] w14; //: /sn:0 {0}(208,496)(208,153)(231,153){1}
//: {2}(235,153)(236,153)(236,146){3}
//: {4}(238,144)(278,144)(278,400){5}
//: {6}(236,142)(236,131){7}
//: {8}(238,129)(311,129)(311,320){9}
//: {10}(236,127)(236,107){11}
//: {12}(233,155)(233,450){13}
wire w19; //: /sn:0 {0}(-703,-375)(-638,-375)(-638,-408)(-615,-408){1}
wire [7:0] w3; //: /sn:0 {0}(233,471)(233,647){1}
//: {2}(235,649)(276,649){3}
//: {4}(280,649)(309,649){5}
//: {6}(313,649)(532,649)(532,554){7}
//: {8}(311,647)(311,341){9}
//: {10}(278,647)(278,421){11}
//: {12}(231,649)(208,649)(208,517){13}
wire w0; //: /sn:0 {0}(274,325)(163,325){1}
//: {2}(159,325)(159,325){3}
//: {4}(155,325)(154,325){5}
//: {6}(150,325)(-147,325){7}
//: {8}(152,327)(152,501)(171,501){9}
//: {10}(157,327)(157,455)(196,455){11}
//: {12}(161,327)(161,405)(241,405){13}
wire w21; //: /sn:0 {0}(-205,445)(-101,445)(-101,335)(274,335){1}
wire w23; //: /sn:0 {0}(161,511)(171,511){1}
wire [7:0] w1; //: /sn:0 {0}(-575,-494)(-575,-458)(-578,-458)(-578,-423){1}
wire w18; //: /sn:0 {0}(-691,-451)(-630,-451)(-630,-418)(-615,-418){1}
wire w22; //: /sn:0 {0}(350,330)(442,330){1}
//: {2}(446,330)(479,330)(479,102)(487,102){3}
//: {4}(444,332)(444,408){5}
//: {6}(442,410)(317,410){7}
//: {8}(444,412)(444,458){9}
//: {10}(442,460)(272,460){11}
//: {12}(444,462)(444,506)(247,506){13}
wire w17; //: /sn:0 {0}(-539,-413)(-499,-413)(-499,-412)(-459,-412){1}
wire w12; //: /sn:0 {0}(186,465)(196,465){1}
wire [7:0] w2; //: /sn:0 {0}(-556,-310)(-556,-309)(-593,-309)(-593,-386)(-578,-386)(-578,-402){1}
//: enddecls
led g4 (.I(w14)); //: @(236,100) /sn:0 /w:[ 11 ] /type:1
//: switch g8 (w21) @(-222,445) /sn:0 /w:[ 0 ] /st:1
register g13 (.Q(w14), .D(w3), .EN(w0), .CLR(w12), .CK(w22)); //: @(233,460) /sn:0 /R:2 /w:[ 13 0 11 1 11 ]
register g3 (.Q(w1), .D(w2), .EN(w18), .CLR(w19), .CK(w17)); //: @(-578,-413) /sn:0 /R:2 /w:[ 1 1 1 1 0 ]
register g2 (.Q(w14), .D(w3), .EN(w0), .CLR(w21), .CK(w22)); //: @(311,330) /sn:0 /R:2 /w:[ 9 9 0 1 0 ]
led g1 (.I(w1)); //: @(-575,-501) /sn:0 /w:[ 0 ] /type:1
//: joint g16 (w14) @(236, 144) /w:[ 4 6 -1 3 ]
//: dip g11 (w3) @(532,544) /sn:0 /w:[ 7 ] /st:8
//: switch g10 (w0) @(-164,325) /sn:0 /w:[ 7 ] /st:1
//: joint g27 (w3) @(233, 649) /w:[ 2 1 12 -1 ]
//: joint g19 (w0) @(157, 325) /w:[ 3 -1 4 10 ]
//: switch g6 (w19) @(-720,-375) /sn:0 /w:[ 0 ] /st:0
clock g9 (.Z(w22)); //: @(500,103) /sn:0 /R:2 /w:[ 3 ] /omega:100 /phi:0 /duty:50
clock g7 (.Z(w17)); //: @(-446,-411) /sn:0 /R:2 /w:[ 1 ] /omega:100 /phi:0 /duty:50
//: joint g20 (w22) @(444, 330) /w:[ 2 -1 1 4 ]
//: joint g15 (w14) @(233, 153) /w:[ 2 -1 1 12 ]
//: joint g25 (w3) @(278, 649) /w:[ 4 10 3 -1 ]
//: joint g17 (w14) @(236, 129) /w:[ 8 10 -1 7 ]
register g14 (.Q(w14), .D(w3), .EN(w0), .CLR(w23), .CK(w22)); //: @(208,506) /sn:0 /R:2 /w:[ 0 13 9 1 13 ]
//: switch g5 (w18) @(-708,-451) /sn:0 /w:[ 0 ] /st:1
//: joint g24 (w3) @(311, 649) /w:[ 6 8 5 -1 ]
//: joint g21 (w0) @(152, 325) /w:[ 5 -1 6 8 ]
//: joint g23 (w22) @(444, 460) /w:[ -1 9 10 12 ]
//: joint g22 (w22) @(444, 410) /w:[ -1 5 6 8 ]
//: dip g0 (w2) @(-556,-320) /sn:0 /w:[ 0 ] /st:5
//: joint g18 (w0) @(161, 325) /w:[ 1 2 -1 12 ]
register g12 (.Q(w14), .D(w3), .EN(w0), .CLR(w7), .CK(w22)); //: @(278,410) /sn:0 /R:2 /w:[ 5 11 13 1 7 ]
endmodule
module regg();
//: interface /sz:(40, 40) /bd:[ ]
wire w19; //: /sn:0 {0}(304,329)(369,329)(369,290)(382,290){1}
wire [7:0] w0; //: /sn:0 {0}(426,167)(426,203)(419,203)(419,275){1}
wire [7:0] w1; //: /sn:0 {0}(504,387)(504,395)(475,395)(475,312)(419,312)(419,296){1}
wire w18; //: /sn:0 {0}(306,254)(367,254)(367,280)(382,280){1}
wire w17; //: /sn:0 {0}(458,285)(542,285){1}
//: enddecls
register g3 (.Q(w0), .D(w1), .EN(w18), .CLR(w19), .CK(w17)); //: @(419,285) /sn:0 /R:2 /w:[ 1 1 1 1 0 ]
led g1 (.I(w1)); //: @(504,380) /sn:0 /w:[ 0 ] /type:1
//: switch g6 (w19) @(287,329) /sn:0 /w:[ 0 ] /st:0
clock g7 (.Z(w17)); //: @(555,286) /sn:0 /R:2 /w:[ 1 ] /omega:100 /phi:0 /duty:50
//: switch g5 (w18) @(289,254) /sn:0 /w:[ 0 ] /st:0
//: dip g0 (w0) @(426,157) /sn:0 /w:[ 0 ] /st:0
endmodule
module divv(s, b, a);
//: interface /sz:(40, 40) /bd:[ ]
input [7:0] b; //: /sn:0 /dp:1 {0}(330,296)(330,260)(397,260)(397,215)(387,215){1}
output [7:0] s; //: /sn:0 {0}(256,410)(237,410)(237,341)(304,341)(304,325){1}
input [7:0] a; //: /sn:0 /dp:1 {0}(298,296)(298,268)(251,268)(251,224)(241,224){1}
wire [7:0] w7; //: /sn:0 {0}(324,325)(324,332){1}
//: enddecls
//: output g3 (s) @(253,410) /sn:0 /w:[ 0 ]
//: input g2 (b) @(385,215) /sn:0 /w:[ 1 ]
div g1 (.A(a), .B(b), .Q(w7), .R(s)); //: @(314,312) /sn:0 /w:[ 0 0 0 1 ]
//: input g0 (a) @(239,224) /sn:0 /w:[ 1 ]
endmodule
Tfe