Old stuff/ecole_etude_fac_de_pau/licence_3/archi/ual.v~
(Deskargatu)
//: version "1.8.6"
module soustr();
//: interface /sz:(40, 40) /bd:[ ]
//: enddecls
endmodule
module additi(s, b, a);
//: interface /sz:(40, 40) /bd:[ ]
input [7:0] b; //: /sn:0 {0}(390,101)(438,101)(438,154)(334,154)(334,181){1}
output [7:0] s; //: /sn:0 {0}(326,294)(318,294)(318,210){1}
input [7:0] a; //: /sn:0 {0}(168,100)(197,100)(197,154)(302,154)(302,181){1}
wire w3; //: /sn:0 {0}(342,195)(470,195){1}
wire w2; //: /sn:0 {0}(235,194)(235,195)(294,195){1}
//: enddecls
//: output g3 (s) @(323,294) /sn:0 /w:[ 0 ]
//: input g2 (b) @(388,101) /sn:0 /w:[ 0 ]
//: input g1 (a) @(166,100) /sn:0 /w:[ 0 ]
add g0 (.A(a), .B(b), .S(s), .CI(w3), .CO(w2)); //: @(318,197) /sn:0 /w:[ 1 1 1 0 1 ]
endmodule
module ual; //: root_module
input [7:0] b; //: /sn:0 {0}(337,61)(385,61)(385,114)(281,114)(281,141){1}
output [7:0] s; //: /sn:0 {0}(273,254)(265,254)(265,170){1}
input [7:0] a; //: /sn:0 {0}(115,60)(144,60)(144,114)(249,114)(249,141){1}
wire w3; //: /sn:0 {0}(289,155)(417,155){1}
wire w2; //: /sn:0 {0}(182,154)(182,155)(241,155){1}
//: enddecls
//: output g3 (s) @(270,254) /sn:0 /w:[ 0 ]
//: input g2 (b) @(335,61) /sn:0 /w:[ 0 ]
//: input g1 (a) @(113,60) /sn:0 /w:[ 0 ]
add g0 (.A(a), .B(b), .S(s), .CI(w3), .CO(w2)); //: @(265,157) /sn:0 /w:[ 1 1 1 0 1 ]
endmodule
module multt(s, b, a);
//: interface /sz:(40, 40) /bd:[ ]
input [7:0] b; //: /sn:0 /dp:1 {0}(235,159)(235,122)(279,122)(279,97)(263,97){1}
output [7:0] s; //: /sn:0 {0}(219,188)(219,271)(245,271){1}
input [7:0] a; //: /sn:0 /dp:1 {0}(203,159)(203,124)(148,124)(148,97)(138,97){1}
//: enddecls
//: output g3 (s) @(242,271) /sn:0 /w:[ 1 ]
mult g2 (.A(a), .B(b), .P(s)); //: @(219,175) /sn:0 /w:[ 0 0 0 ]
//: input g1 (b) @(261,97) /sn:0 /w:[ 1 ]
//: input g0 (a) @(136,97) /sn:0 /w:[ 1 ]
endmodule
module regg();
//: interface /sz:(40, 40) /bd:[ ]
wire [7:0] w14; //: /sn:0 {0}(308,186)(308,176){1}
wire w19; //: /sn:0 {0}(193,209)(258,209)(258,170)(271,170){1}
wire w18; //: /sn:0 {0}(195,134)(256,134)(256,160)(271,160){1}
wire w17; //: /sn:0 {0}(347,165)(431,165){1}
wire [7:0] w13; //: /sn:0 {0}(308,155)(308,95){1}
//: enddecls
register g3 (.Q(w13), .D(w14), .EN(w18), .CLR(w19), .CK(w17)); //: @(308,165) /sn:0 /R:2 /w:[ 0 1 1 1 0 ]
//: switch g6 (w19) @(176,209) /sn:0 /w:[ 0 ] /st:0
clock g7 (.Z(w17)); //: @(444,166) /sn:0 /R:2 /w:[ 1 ] /omega:100 /phi:0 /duty:50
//: switch g5 (w18) @(178,134) /sn:0 /w:[ 0 ] /st:0
endmodule
module divv(s, b, a);
//: interface /sz:(40, 40) /bd:[ ]
input [7:0] b; //: /sn:0 /dp:1 {0}(330,296)(330,260)(397,260)(397,215)(387,215){1}
output [7:0] s; //: /sn:0 {0}(256,410)(237,410)(237,341)(304,341)(304,325){1}
input [7:0] a; //: /sn:0 /dp:1 {0}(298,296)(298,268)(251,268)(251,224)(241,224){1}
wire [7:0] w7; //: /sn:0 {0}(324,325)(324,332){1}
//: enddecls
//: output g3 (s) @(253,410) /sn:0 /w:[ 0 ]
//: input g2 (b) @(385,215) /sn:0 /w:[ 1 ]
div g1 (.A(a), .B(b), .Q(w7), .R(s)); //: @(314,312) /sn:0 /w:[ 0 0 0 1 ]
//: input g0 (a) @(239,224) /sn:0 /w:[ 1 ]
endmodule
Tfe