Old stuff/ecole_etude_fac_de_pau/licence_3/archi/mips/dlx.html
(Deskargatu)
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<head><title>DLX ISA ref</title></head>
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<h1>DLX ISA ref</h1>
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<tr><td width=150><b>op</b><td><b>inst</b><td><b>notes</b>
<tr><td>0x00 000000<td><td>i-format instruction
<tr><td>0x01 000001<td><td>floating-point instruction (ignore)
<tr><td>
<tr><td colspan=3><b>jump</b>
<tr><td>0x02 000010<td>j label<td>absolute addressing
<tr><td>0x03 000011<td>jal label<td>$31 <- PC
<tr><td>
<tr><td colspan=3><b>branch</b>
<tr><td>0x04 000100<td>beqz $r1, label<td>PC+4-relative addressing
<tr><td>0x05 000101<td>bnez $r1, label
<tr><td>0x06 000110<td>bfpt<td>floating-point, not implemented
<tr><td>0x07 000111<td>bfpf
<tr><td>
<tr><td colspan=3><b>ALU immediate</b>
<tr><td>0x08 00<b>1000</b><td>addi $rd, $rs, immed
<tr><td>0x09 00<b>1001</b><td>addui
<tr><td>0x0a 00<b>1010</b><td>subi
<tr><td>0x0b 00<b>1011</b><td>subui
<tr><td>0x0c 00<b>1100</b><td>andi $rd, $rs, immed<td>$rd = $rs & immed
<tr><td>0x0d 00<b>1101</b><td>ori
<tr><td>0x0e 00<b>1110</b><td>xori
<tr><td>0x0f 00<b>1111</b><td>lhi $rd, immed<td>$rd[31:16] = immed[15:0]
<tr><td>
<tr><td colspan=3><b>Exceptions</b>
<tr><td>0x10 010000<td>rfe<td>not yet
<tr><td>0x11 010001<td>trap<td>not yet
<tr><td>
<tr><td colspan=3><b>jump register</b>
<tr><td>0x12 010010<td>jr $31
<tr><td>0x13 010011<td>jalr $29<td>$31 <- PC
<tr><td>
<tr><td colspan=3><b>ALU: shift immediate</b>
<tr><td>0x14 01<b>0100</b><td>slli
<tr><td>0x15 01<b>0110</b><td>srli
<tr><td>0x16 01<b>0111</b><td>srai
<tr><td>
<tr><td colspan=3><b>Set-on-condition immediate</b>
<tr><td>0x18 011<b>000</b><td>seqi $rd, $r1, $r2<td>$rd <- 1 if $r1==$r2
<tr><td>0x19 011<b>001</b><td>snei
<tr><td>0x1a 011<b>010</b><td>slti
<tr><td>0x1b 011<b>011</b><td>sgti
<tr><td>0x1c 011<b>100</b><td>slei
<tr><td>0x1d 011<b>101</b><td>sgei
<tr><td>
<tr><td colspan=3><b>load/store (aligned only)</b>
<tr><td>0x23 100011<td>lw $reg, offset($rbase)<td>$reg <- Mem[$rbase+offset]
<tr><td>0x2b 101011<td>sw $reg, offset($rbase)<td>Mem[$rbase+offset] <- $reg
<tr><td>
<tr><td colspan=3><b>Set-on-condition immediate unsigned</b>
<tr><td>0x30 110<b>000</b><td>sequi
<tr><td>0x31 110<b>001</b><td>sneui
<tr><td>0x32 110<b>010</b><td>sltui
<tr><td>0x33 110<b>011</b><td>sgtui
<tr><td>0x34 110<b>100</b><td>sleui
<tr><td>0x35 110<b>101</b><td>sgeui
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<h2>Function field for r-format instructions</h2>
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<tr><td width=150><b>op</b><td><b>inst</b><td><b>notes</b>
<tr><td>0x00 000000<td>nop
<tr><td>
<tr><td colspan=3><b>ALU: shift</b>
<tr><td>0x04 00<b>0100</b><td>sll
<tr><td>0x06 00<b>0110</b><td>srl
<tr><td>0x07 00<b>0111</b><td>sra
<tr><td>
<tr><td colspan=3><b>Set-on-condition unsigned</b>
<tr><td>0x10 010<b>000</b><td>sequ
<tr><td>0x11 010<b>001</b><td>sneu
<tr><td>0x12 010<b>010</b><td>sltu
<tr><td>0x13 010<b>011</b><td>sgtu
<tr><td>0x14 010<b>100</b><td>sleu
<tr><td>0x15 010<b>101</b><td>sgeu
<tr><td>
<tr><td colspan=3><b>ALU</b>
<tr><td>0x20 10<b>0000</b><td>add $rd, $r1, $r2
<tr><td>0x21 10<b>0001</b><td>addu
<tr><td>0x22 10<b>0010</b><td>sub
<tr><td>0x23 10<b>0011</b><td>subu
<tr><td>0x24 10<b>0100</b><td>and
<tr><td>0x25 10<b>0101</b><td>or
<tr><td>0x26 10<b>0110</b><td>xor
<tr><td>
<tr><td colspan=3><b>Set-on-condition</b>
<tr><td>0x28 101<b>000</b><td>seq $rd, $r1, $r2
<tr><td>0x29 101<b>001</b><td>sne
<tr><td>0x2a 101<b>010</b><td>slt
<tr><td>0x2b 101<b>011</b><td>sgt
<tr><td>0x2c 101<b>100</b><td>sle
<tr><td>0x2d 101<b>101</b><td>sge
<tr><td>
<tr><td colspan=3><b>Others</b>
<tr><td colspan=3>Not going to implement mov instructions or FP instructions.
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